In order to properly recover the data contained in a received signal a data communications receiver, such as a modem, must synchronize its baud clock with the baud clock of the remote transmitter. Typically, the clock in the local device and the clock in the remote device will both be crystal controlled and therefore the local baud clock and the remote baud clock, even without a synchronization circuit, typically differ less than 0.02 percent in frequency. However, even with this small offset in frequency, the cumulative phase difference between the two baud clocks eventually becomes large enough to cause errors in the data transfer.
Modern modems use an analog-to-digital (A/D) converter to periodically sample the received analog signal and convert it to a digital format to provide a sampled, digitized signal, and one or more microprocessors to process the digitized signal and recover the data being transferred. Two types of sampling clocks for the A/D converters are used: a variable frequency sampling clock; and a fixed frequency sampling clock. When a variable frequency sampling clock is used the recovered baud clock is used to adjust the frequency and/or phase of the sampling clock so that the sampling frequency, when divided by the appropriate number (typically an integer), yields the baud frequency and causes the local baud clock to be locked on to the remote baud clock.
Fractionally spaced adaptive equalizers can readily compensate for timing-phase variations between the remote transmitter baud clock and the receiver baud clock. When there is a frequency difference between these clocks the equalizer compensates for the accumulated timing-phase difference by shifting the equalizer tap weights in the appropriate direction along the delay line. The spatial distribution of the equalizer coefficients can be used to adjust the receiver sampling frequencies so that the local and remote baud clocks are synchronized. The common envelope-derived timing recovery system is replaced with a closed-loop center-tap tracking algorithm. The receiver is locked to the transmitter in a closed-loop manner by observing the distribution of the equalizer tap weights. The receiver sampling clock is then adjusted so as to maintain the dominant tap weights in the center of the equalizer. However, in order to obtain the desired frequency and/or phase resolution for the sampling clock, a very high frequency master clock is typically used in conjunction with a programmable divider chain which provides the sampling clock. Typically, this divider chain and/or the sampling clock are used to generate other clocks used by the modem. Therefore, adjusting the frequency and/or phase of the sampling clock frequently requires that additional steps be taken to prevent or compensate for changes in frequency of these other clocks.
With a fixed sampling clock frequency the sampled, digitized signal is interpolated to a high sampling rate and then decimated down to the signal processing rate under the control of a timing function. The timing function determines which of the interpolated samples correspond to the optimal sampling points and are to be used. An envelope-derived timing recovery system is typically used with this technique. However, the envelope-derived timing recovery technique can be plagued by considerable timing jitter, especially when the channel bandwidth is fully used by a narrow roll-off system or when the channel is severely attenuated at the band edge.
Therefore, there is a need for a baud timing recovery scheme which provides for the use of a fixed frequency for the sampling clock but does not use envelope-derived timing recovery.
There is also a need for a baud timing recovery scheme which uses a fractionally spaced adaptive equalizer to lock the local receiver baud timing to the remote transmitter baud timing without having to adjust the frequency of the sampling clock.